AMD's Zen 6c Beats Zen 6 Per Clock, Despite Being the Dense Core
AMD's Zen 6 Family: Feeding the Beast
A deep dive into AMD's Zen 6 and Zen 6c cores, measured on EPYC 9686F and EPYC 9996 silicon. Zen 6 is a bigger rework than Zen 5 suggested, with faster branch recovery, dual decode clusters usable by one thread, and fixed L2 bandwidth. The surprise: Zen 6c carries larger out-of-order structures and a 128 MB L3, so at matched 4.1 GHz it leads Zen 6 by about 6.7% in integer and 4% in floating point.
The differences suggest that AMD is specializing the two designs. Zen 6 appears tuned for high frequency, while Zen 6c has more capacity to tolerate comparatively high memory latency.
- bmenrigh
The worst thing about consumer (AM5) Zen4 and Zen5 is the I/O die chiplet and memory controller on it. I've heard they're finally going to ship a new I/O chiplet in Zen6 on a much smaller node. Their existing AM5 Zen4/5 memory controller when using both memory channels is terrible. Extremely hard or impossible to get above 3600 MT/s.
Of all the things I'm looking forward to on Zen6, an improved memory controller is at the top of the list.
Edit: and yes, others may say the paltry few PCIE 5.0 lanes is the worst thing about AM5, but that doesn't affect my usage much, and unfortunately I think that's a limitation of AM5 itself rather than the I/O chiplet.
- joebonrichie
The instruction level parallelism in the 2-ahead branch prediction is super cool stuff, I know zen5 had this feature but it's kind of crazy that memory is so slow relative to the cores that this complexity is beneficial and worthwhile.
- Aardwolf
> AMD has reduced the number of integer multiply units from three to two, with PDEP and PEXT throughput also falling from three instructions per cycle to two.
Are PDEP and PEXT using the same (parts of) circuits as multiply (they are very different operations...), or are this just two independent drops of circuitry and the wording is just a bit unclear?
- Remnant44
What looks like a lot of small balanced improvements to the core itself. Four vector loads per cycle at 256b of less, I wonder if the gather performance is finally acceptable? Another balance example, they actually reduced the number of integer multipliers down to two. I wonder if that was to make diespace for the vnni pipes?
The real star looks like the c cores though. 32 C cores per chiplet with increased l3 cache is impressive
- bee_rider
32 cores is a lot of cores in a CCD. Is there a there any smaller logical unit between a CCD and a core, or are you expected to wrangle 32 cores in your lowest NUMA level?
- lp92
Seems like they are starting to optimize the C core architecture already. Wonder how long it'll be before it becomes its own line up and branding.
- sylware
When you look at all this prediction, it is so much important for a 'core/smt' to 'learn' some code behaviour, hence thread CPU/SMT affinity is beyond paramount for applications which are pushing a bit our CPUs.
- spwa4
One thing I wonder about is that these CPUs are just so much faster than their memory controllers. So why not add more? Why don't they have a memory controller per core, for example?