A Student Built an Out-of-Order RISC-V CPU from Scratch in Bluespec
Building an Order RISC-V CPU from scratch
Bored with his engineering courses, a student set out to replicate the out-of-order execution inside his Ryzen 9 laptop. The result, Specula, is a 32-bit speculative RISC-V core written in Bluespec SystemVerilog, with register renaming, a 32-entry reorder buffer, a gshare branch predictor, and Sv32 virtual memory. It also boots xv6 and synthesizes for an Artix-7 FPGA. The write-up walks through the frontend, dispatch, and retirement machinery in plain language.
The way I learn is to read about something, and try and replicate it to see what falls apart along the way, as that moment teaches far more than any theoretical class a person could attend.
- Joker_vD
For a general reference, here [0] (PDF) is a somewhat detailed description (that is, it actually discusses how this particular implementation solves the problems that arise before it) of an out-of-order implementation for a simplistic RISC ISA. Suffice to say, it doesn't really have all that much in common with the classical 5-stage RISC pipeline.
- Narishma
Title should be "Out of Order RISC-V core from scratch - Specula". Don't know why it was changed.
- lp92
> 11.9 MHz (meaning it is as slow as a herd of snails traveling through peanut butter)
To be fair, this is almost 6x faster than the Apollo Guidance Computer and running on hardware accessible for a low cost.