Student builds a VGA driver in SystemVerilog on a $100 FPGA board
Making a VGA Driver in SystemVerilog
A digital logic lab project that walks through creating a VGA driver in SystemVerilog on the DE10-lite FPGA. It covers generating a 25 MHz pixel clock from the board's 50 MHz clock, implementing horizontal and vertical counters for sync signals, mapping 10 switches to 12-bit color, and loading an image from ROM with alpha compositing. The author spent over 10 hours debugging timings and rewrote a Python tool in Go for cross-platform image conversion.
At this point in the lab I estimate that I had spent well over 10+ hours working on getting the timings to be correct and going down a few wild goose chases that only proved that I had to rework parts of my design.