Why Every DDR3+ Interface Must Be Tuned at Boot
The DRAM interface and the PHY (why a DDR3+ interface must be tuned at boot)
The DRAM interface splits into a shared command/address bus and per-byte-lane data paths with source-synchronous strobes. Fly-by routing skews the clock across chips, so write leveling, DQ-DQS training, and read leveling must run at boot to align each lane. LiteDRAM implements these calibrations in its PHYs and BIOS, with termination and ZQ calibration handled via mode registers.
With fly-by routing the skew between the first and the last chip can exceed a clock period, so each lane needs its own DQS delay.