Why Your AArch64 Spin Lock Crashes on Real Hardware but Not in QEMU
When Ldaxr Doesn't Work: Exclusive Accesses and Cacheability on AArch64
I built a spin lock for my hobby OS, floss, using ldaxr/stxr. It ran flawlessly in QEMU but threw a Data Abort on a Raspberry Pi 5. The culprit: the SCTLR.C bit was disabled, making memory non-cacheable. Exclusive accesses require Write-Back cacheable memory. Enabling cacheability fixed it, and I confirmed that Write-Through or Non-cacheable attributes also fail.
When the data cache is disabled, all load and store instructions to cacheable memory are treated as if they were Non-cacheable and are incoherent with the caches in both this core and other cores in the cluster.