A 16-core chip bets on hexagonal wiring to cut cost and power
Chip-hex:cost-benefit, energy efficiency and hexagonal
LUNZ HEX-16 is an early-stage, pre-silicon research project asking whether 16 simple in-order cores linked by a hexagonal network-on-chip can deliver a better performance-per-watt and performance-per-cost trade-off than conventional designs. It ships an architectural spec and a Python simulator, excludes AI/GPU accelerators, and weighs 14 KiB versus 16 KiB L1 caches. All results are simulation estimates, not silicon measurements.
Can a carefully balanced 16-core architecture achieve useful performance with lower energy consumption and implementation cost, without relying on large specialized accelerators?