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A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better"
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- ndiddy
I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC-V is great for embedded because companies can build it into custom chips with specifically the functionality they need, and because of how cheap it is for low-end use cases since there's no license fees.
The only real point of contention I see between the two is that this piece goes on to talk about how it's a selling point that RISC-V can be used for both low-end 10 cent microcontrollers, and high-end multi-core processors running Linux. Personally I don't see the benefit of this since you're going to have to recompile your software anyway, and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
- kelnos
I don't really understand the author's conclusions about cost and shipping, and how RISC-V is cheaper and more accessible to people outside the US and Europe. He first talks about how getting $1 worth of chips can cost $60-$200 in shipping for him due to his location... but then by the end claims that RISC-V gives him "an architecture that arrives in my country at ten cents a part".
I don't get how both things can be true. The cost to ship something to Trinidad and Tobago has nothing to do with whether it's ARM or RISC-V; shipping the same weight of either kind of chips should cost exactly the same amount. Yes, maybe the chip cost itself of a particular ARM-based model is $0.15 while the equivalent RISC-V chip costs $0.10, but if the issue (for him and other people who live outside US/Europe) is that shipping costs are orders of magnitude more expensive than the thing being shipped, that chip-cost difference becomes irrelevant.
I think he does make a great point about how fragmentation does give you better optionality: ARM is sort of like cable TV where you have a small number of product categories that each bundle a particular set of features, whereas with RISC-V you design something bespoke that does exactly what you need and nothing more. But again, this isn't going to affect shipping costs.
- vlovich123
He says:
> From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings
Yet earlier:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
Seems to me that the difference between a 10c chip and a $1 chip are a rounding error when the shipping cost dominates so much?
- HawtAds
I love the article, it's a breath of fresh air compared to the usual bay area centric takes. However there's just one issue:
> The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh
It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile delivery costs are fairly low there too.
- strenholme
I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64.
This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86 computers of the era.
However, people were buying x86 computers at a far higher rate, giving Intel (and AMD) the money needed to invest in better chip designs and better fabs. Linux was, at the same time, gaining traction and, around the time the dot-com bubble popped and there were no longer companies with the money needed to get Sun SPARC workstations (or what not) at $50,000 or more a pop to start up a web business, x86 computers running Linux had nearly the same performance at a much lower price. Once the Itanium sank and x86_64 was mainstream, x86_64 was the ISA of choice for performance workstations and servers, and the RISC ISAs that survived were now mainly used in the embedded space. Indeed, ARM was never a high performance RISC processor, and it was the one that took over the embedded space while PA-RISC, Alpha, and SPARC died.
The ISA for what were cheap computers become the highest performance ISA around.
It has been only in the 2020s that RISC processors have gotten x86_64 levels of performance, notably in the the Apple M series of processors. […]
- kazinator
> He derives the case for the chip and then spends the rest of the article annoyed that the chip exists. This is almost satirical.
His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?
- codedokode
I disagree with some points in "RISC-V They Should Have Known Better".
For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM is better because it has a "store multiple registers" instruction. It wouldn't help because storing multiple registers still requires multiple bus cycles, and microcontroller probably has a 32-bit bus and no cache, so saving N registers requires N memory cycles - no matter, is it done with a single instruction (ARM), or with multiple (RISC-V). And implementing this ARM instruction makes the core more complicated with little benefit.
As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment.
The real weak points of RISC-V are:
- no trap on integer overflow and invalid FP results . Overflows cause vulnerabilities
- no optimizations for fast context switch, which is required for dumping legacy unsafe monolithic kernels, especially in age of AI actively searching for vulns
- weird vector extensions
- avmich
To me it feels like the difference in positions is "this could be made better" vs. "but this is already so much better than before". Both are right.
Maybe I'm missing something important so far...
- ghostly_s
I lost the thread of his argument when he brought up the shipping expense:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
then follows with:
> the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings.
When shipping is so expensive, doesn't the difference between $1 and $.10 unit cost become less relevant?
- hn_submit
Grinberg's article is highly technical and compares RISC-V to other ISAs like MIPS, x86 and ARM. This article is more about the freedom RISC-V offers, both in licensing, availability, flexibility and cost.
RISC-V has put enormous pricing pressure on manufacturers like MicroChip, which is now offering its AVR line of 8-bit MCUs for pennies a piece. Too bad that the 32-bit RISC-V offerings from, among others, WCH are far more powerful at a similar price point.