RISC-V: Why the Open ISA Falls Short for Both Cheap Chips and Supercomputers

RISC-V: They should have known better

Dmitry.GR argues that RISC-V's one-size-fits-all ISA is fundamentally flawed. For cheap microcontrollers, its interrupt handling and compressed instructions are worse than the decade-old Cortex-M0. For high-end cores, it lacks addressing modes for array access, forcing three instructions where one would do. The author calls out the RISC-V community's excuses, like instruction fusion, as unrealistic, and notes that proposed extensions like Zba came years too late.