FastLanes UTL: A SIMD-Friendly Layout for Delta Decoding
The FastLanes Unified Transport Layout
David Anderson explains the FastLanes Unified Transport Layout (UTL), a data permutation designed to make delta encoding and decoding highly data-parallel. The post derives UTL step-by-step, showing how to arrange 1024 values so that SIMD registers can process multiple independent delta streams simultaneously, regardless of element size (64-bit, 32-bit, 16-bit, or 8-bit). It also discusses the trade-offs in memory access patterns and why they don't hurt performance in practice.
The parts of FastLanes we’re interested for this post aim to add parallelism to the problem, so that we can use SIMD to make delta encoding and (especially) decoding very fast.