Assembly Hall of Shame: Racing to the Bottom of CPU Performance
This GitHub repository flips instruction latency analysis on its head, hunting for the absolute slowest single instructions on x86 CPUs. Using clever tricks like MMIO reads from PCIe fabric and microcode assists, the project times instructions like `fxrstor64` and `vmovdqu`, with the current champion taking 62 seconds. The leaderboard ranks instructions from `nop` (1 cycle) to the champion (198 billion cycles), showcasing the extremes of CPU performance.
The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
- Retr0id
Related, and linked in the readme: https://github.com/xoreaxeaxeax/smiiiiiiiiiiiiiiii (using the slow instructions to break SMI)
- monocasa
It says in the rules
> Trapped/emulated/virtualized instructions may only time the trap, not the handler.
But I feel like that 12ms write to an ACPI IO port at current leaderboard position 8 is probably trapping to SMM and being handled there.
- layer8
Nop should be #1, because it is infinitely slow for what it does. ;)
- TomatoCo
This author also has other things like: A compiler that emits only `mov` instructions and another compiler that deliberately messes with the control flow so that, if disassembled, common debuggers will draw symbols like skulls or threats. https://github.com/xoreaxeaxeax/repsych
- markus_zhang
Does that mean Chris Domas is ready for his next adventure?